Direct Growth of Highly Conductive Large‐Area Stretchable Graphene

Abstract The direct synthesis of inherently defect‐free, large‐area graphene on flexible substrates is a key technology for soft electronic devices. In the present work, in situ plasma‐assisted thermal chemical vapor deposition is implemented in order to synthesize 4 in. diameter high‐quality graphene directly on 10 nm thick Ti‐buffered substrates at 100 °C. The in situ synthesized monolayer graphene displays outstanding stretching properties coupled with low sheet resistance. Further improved mechanical and electronic performances are achieved by the in situ multi‐stacking of graphene. The four‐layered graphene multi‐stack is shown to display an ultralow resistance of ≈6 Ω sq−1, which is consistently maintained during the harsh repeat stretching tests and is assisted by self‐p‐doping under ambient conditions. Graphene‐field effect transistors fabricated on polydimethylsiloxane substrates reveal an unprecedented hole mobility of ≈21 000 cm2 V−1 s−1 at a gate voltage of −4 V, irrespective of the channel length, which is consistently maintained during the repeat stretching test of 5000 cycles at 140% parallel strain.


Supporting Tables and Figures
TiO2-x as well as an adsorption onto the graphene films (O1s).

Fig. 7
Arrhenius plot of the graphene growth rate at different temperatures for a mechanism of graphene growth.

Deposition of Ti on PET and PDMS substrates, and subsequent analysis
The 10  Therefore, in this study, thickness of the Ti-buffer layer was determined at 10 nm for graphene growth.
The electronic state of Ti-buffer layer deposited under an argon and hydrogen atmosphere  Fig. 15b).
The thickness of the Ti layer was confirmed via transmission electron microscopy (TEM) and AFM cross-sectional imaging. Sheet resistance and transmittance were measured using a Z-theta method and a UV-vis spectrometer, respectively. The rms roughness of Ti films annealed at different temperatures under a hydrogen atmosphere was measured via AFM (MFP-3D-BIO, Asylum Research) at room temperature to examine their thermal stability. The Ti before and after graphene growth was investigated via X-ray photoelectron spectroscopy (XPS).

Large-area graphene synthesis at low temperatures via PATCVD on Ti-buffered substrates and subsequent analysis
Large-area mGr (4-in-wafer) was synthesized at low temperatures via PATCVD. After depositing Ti, PATCVD was performed for mGr growth under the following optimal conditions: rf power of 70 W, base pressure of 1.3 10 -4 Pa, working pressure of 2.4 10 2 Pa, growth time of 2h, a gas flow rate of Ar/H2/CH4 : 10/25/3.0 sccm (standard cc min -1 ), a distance between the rf sources of 8 cm, and a distance of 10 cm between the rf sources and a substrate (see Fig.   1A). The growth temperature was controlled under 150 °C.
The electronic state of the 10-nm-thick Ti films synthesized via dc sputtering was analyzed via XPS without breaking the vacuum. The XPS spectra was obtained using an AXIS Ultra-DLD (Kratos Inc.) with a monochromatic Al Kα X-ray (hν = 1486.6 eV), which was located at the Korea Basic Science Institute (KBSI). The XPS analyzer was connected to a high-vacuum dc/rf (radio-frequency) sputter system via an ultra-high vacuum chamber, which allowed us to measure the Ti 2p spectrum of Ti thin films without exposing the sample to air. After subtraction of the Shirley background, the Ti 2p spectrum was fitted using Doniach-Sunjic functions with an asymmetric line-shape. [46] For annular dark field (ADF)-TEM analysis of mGr, a 200-nm-thick SiO2 layer was deposited on mGr that was free of plasma damage via facing-target sputtering before the sample preparation via focused ion beam (FIB). The crystallinity of the graphene was determined via high-resolution TEM (HRTEM) and the selected area electron diffraction (SAED) patterns of the mGr were acquired from the mGr transferred to a copper grid using a damage-mitigated dry transfer process (Supporting Fig. 2). [47] In order to exclude the effect of the 10 nm-thick TiO2x layer on the sheet resistance and mobility of the graphene, graphene grown directly onto the 10 nm-thick Ti-buffered Cu foil was transferred to the SiO2(100nm)/Si substrate after etching for 24h. The complete etching of the TiO2-x layer was performed for several minutes using a BOE (NH4F: HF = 6:1) solution after Cu foil etching for 24h.
The transmittance of monolayer graphene was measured via UV-vis spectrometer. The sheet resistance of the graphene was measured via the Z-theta method using an impedance/gain-phase analyzer (HP4194A) in a range of 100 Hz-10 MHz.
To estimate the domain size of mGr using 5CB (4-pentyl-4'-cyanobiphenyl), liquid-crystal films (< 2 μm) were spin-coated onto the graphene films at 500-3,000 rpm. The textures of the liquid-crystals oriented on the graphene film were observed using a polarized optical microscope (POM, LV 100POL, Nikon) equipped with a 1λ wave plate and a charge-coupled device (CCD) camera.

Structural analysis of mGr
A mGr was transferred to a SiO2/Si substrate (for XPS analysis) and a Cu grid (for HRTEM analysis) to investigate a high-quality mGr lattice without an underlying TiO2-x layer. The transfer of mGr grown at 100 C on a Ti-buffered Cu foil was performed for 24h via dry etching process using a carrier film (sequential etching process of Supporting Fig. 2) without surface modifications, and then a residual TiO2-x layer was completely removed using a buffered oxide etch (BOE) solution. An XPS wide scan (Supporting Fig. 3a) of the transferred graphene showed neither Ti nor TiO2-x peaks, which revealed a pure pristine graphene after transfer. The existence of an oxygen on the transferred graphene (Supporting Fig. 3a) was attributed to an adsorption of oxygen onto the graphene under ambient air. Based on the high-resolution TEM image (Supporting Fig. 3b) and a selected-area electron diffraction (SAED) pattern (inset of Supporting Fig. 3b) show the atomically thin, high-quality mGr lattice.

Graphene-FET synthesis
The graphene bottom-gated-FET devices were prepared with different channel lengths from 10 to 100 m at a channel width of 20 m via a photolithography process. A 120 nm-thick polyimide gate insulator was deposited onto the gate electrode (graphene/TiO2-x)/PDMS via spin coating. The polyimide insulators used in this study were synthesized using hexafluoroisopropylidenediphthalic anhydride (6FDA) and 4,4-methylenedibenzenamine (MDA) monomers in m-cresol solvent, as described in our previous reports. [43,44] The source/drain graphene electrode and graphene active layer were in-situ grown onto the gate insulator (PI).

Mobility analysis
A mGr active layer was grown on Ti (10 nm)-buffered PI (120 nm) gate insulator at 100 C.
The structure of the bottom-gated FETs is as follows: Source/Drain electrode (GTO)/graphene active layer (GTO)/gate insulator (PI)/gate electrode (GTO)/PDMS substrate. Because the contact resistance may influence the mobility, we used a gated-transfer line method (gTLM) for FET-mobility calculation, which showed a relationship between channel length and channel resistance.
In the linear regime (Fig. 4B), for fixed VGS, RTOT (total resistance) was calculated by VDS/ID, and RTOT = Rch (L) + Rc (contact resistance). For determination of Rc, when the RTOT was plotted against L for various VGS (Supporting Fig. 12a), a straight line is obtained and it was intercepted at y-axis (Supporting Fig. 12b). The intercepted value is 2Rc. The channel resistance for holes and electrons has a direct linear relationship with the channel length, which reveals an increase in the channel resistance with increases in the channel length at VGS = 4V (Supporting Fig.   12c). For determination of VTH, the reciprocal slopes (( RTOT/ L) -1 ) were plotted against VGS and a straight line was extrapolated to x-axis, an intercept at x-axis was a value of VTH (Supporting Fig. 12d). The various parameters such as RTOT, Rc, and RCH for different channel lengths at a channel width of 20 m were summarized at Supporting Table 1 (for hole) and

Stretching tests
The

Density functional theory calculations
The Ti(0001) lattice was modeled with a 6 6 3 slab. A 15 Å of vacuum space was secured to describe the surface. The bottom Ti layer was fixed during optimization, and a single graphene layer composed of 72 carbon atoms was optimized on the Ti(0001) lattice. The details of sequential monolayer graphene (mGr) formation on Ti(0001) can be found in our previous report. [22] To describe the TiO2-x substrate, total 32 oxygen atoms were added to the upper two atomic layers of the Ti slab. The interaction between mGr and TiO2-x was estimated by optimizing a mGr layer (composed of 72 carbon atoms) on the optimized TiO2-x surface.
We performed GGA (Generalized Gradient Approximation) levels of spin-polarized DFT calculations with the Vienna ab-initio simulation package (VASP) [48] and the Perdew-Burke-Ernzerhof (PBE) functional. [49] Plane waves up to an energy cutoff of 400 eV were used to describe the valance electrons. The projector augmented wave method was applied to describe the interactions between core ions and valance electrons. [50] The Brillouin zone was sampled at the -point. The convergence criteria for the electronic structure and the geometry were 10 - Pre-processing data of Fig. 3G (at 10 4 cycles)

Data presentation and sample size
1) The estimated intensity ratio of I 2D /I G and I D /I G : The error ranges were determined using Raman beam size of 3 m, measurement frequency of 20 times at 500 m intervals, and beam intensity of 100 mW in sample size of 2 2 cm 2 .
2) The error ranges of sheet resistance: The error ranges were determined by measurements of 20 times in sample size of 2 2 cm 2 .

Statistical methods for determination of graphene domain size and software: Domain
size and distribution were determined by measurements above 80 domains in 2 2 cm 2 sample size. Determination of average domain size was performed by a standard deviation method using Excel File of computer.